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Engineer, ASIC DvDs Eng Sr. Jobs LSI , F\W Development Engineer, ASIC
DvDs Eng Sr. Jobs LSI , F\W Development Engineer, ASIC DvDs Eng Sr. Jobs LSI
F\W Development Engineer
Qualifications:
Bachelors degree in Electronics / Computer Science from a premier college / university.
Excellent Programming knowledge in C/C++.
Good understanding of Operating systems, Data Structures, Interprocess communication.
Desirable knowledge of Scripting languages Perl/Python/Tcl.
Location: Pune
ASIC DvDs Eng Sr.
Qualifications: Masters in Engineering/ Bachelors in Engineering from a reputed institute with good academic record. Experience: 3 to 8+ years of experience and should have executed P & R for large chip designs.
Location: Bangalore
ASIC DvDs Engineer 2
Qualifications:
MSEE or equivalent with 2-5 years.
Knowledge of ASIC design and implementation. Familiar with Verilog RTL coding, Verilog Simulators (NC or VCS) , Synopsys Design Compiler, Synopsys ICC Physical design tools, Prime Time for Static Timing Analysis, Mentor Fast Scan, Logic Vision, Verplex (or Formality), and scripting.
Location: Bangalore
Engineering Manager ASIC\ASSP physical design implementation
Qualifications: Masters in Engineering/ Bachelors in Engineering from a reputed institute with good academic record.
Experience:
10+ years of relevant experience in ASIC/ASSP physical design implementation.
Proven record of leading physical design implementation team(s), for at least 4 to 5 tapeouts.
Location: Bangalore
P3
Qualifications: BE /M E. - EEE / ECE.
Experience: 5-10 years.
Location: Pune
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F\W Development Engineer
Qualifications:
Bachelors degree in Electronics / Computer Science from a premier college / university.
Excellent Programming knowledge in C/C++.
Good understanding of Operating systems, Data Structures, Interprocess communication.
Desirable knowledge of Scripting languages Perl/Python/Tcl.
Location: Pune
ASIC DvDs Eng Sr.
Qualifications: Masters in Engineering/ Bachelors in Engineering from a reputed institute with good academic record. Experience: 3 to 8+ years of experience and should have executed P & R for large chip designs.
Location: Bangalore
ASIC DvDs Engineer 2
Qualifications:
MSEE or equivalent with 2-5 years.
Knowledge of ASIC design and implementation. Familiar with Verilog RTL coding, Verilog Simulators (NC or VCS) , Synopsys Design Compiler, Synopsys ICC Physical design tools, Prime Time for Static Timing Analysis, Mentor Fast Scan, Logic Vision, Verplex (or Formality), and scripting.
Location: Bangalore
Engineering Manager ASIC\ASSP physical design implementation
Qualifications: Masters in Engineering/ Bachelors in Engineering from a reputed institute with good academic record.
Experience:
10+ years of relevant experience in ASIC/ASSP physical design implementation.
Proven record of leading physical design implementation team(s), for at least 4 to 5 tapeouts.
Location: Bangalore
P3
Qualifications: BE /M E. - EEE / ECE.
Experience: 5-10 years.
Location: Pune
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